Ш1ллддллддллллддллллг, Toshiba – Toshiba TMP87CP24AF User Manual
Page 78
Attention! The text in this document has been recognized automatically. To view the original document, you can use the "Original mode".
TOSHIBA
TMP87CM24A/P24A
(2)
Event Counter Mode
In this mode, the TC3 pin input pulses are used for counting up. Either the rising or falling edge can
be
selected
with
INT3ES
(bit
3
in
EINTCR).
The
contents
of
TREG3A
are
compared
with
the
contents
of
the
up-counter.
If
a
match
is
found,
an
INTTC3
interrupt
is
generated
and
the
counter
is
cleared.
The
maximum
applied
frequency
is
fc/2^
[Hz]
in
the
NORMAL1/2
or
IDLE1/2
mode,
and
fs/2^
[Hz]
in
SLOW
or
SLEEP
mode.
Two
or
more
machine
cycles
are
required
for
both
the
"H"
and
"L"
levels
of
the pulse width.
The
current
contents
of
up-counter
are
loaded
into
TREG3B
by
setting
SCAP
(bit
6
in
TC3CR)
to
"1".
SCAP is automatically cleared after capturing.
Example : Generates an interrupt every 0.5 s, inputing 50Hz pulses to the TC3 pin.
LD (TC3CR), 00001100B
LD (TREG3A), 19H
LD (TC3CR), 00011100B
Sets TC3 mode and source clock
0.5 s^ 1/50 = 25=
19
h
Start TC3
(3)
Capture Mode
The pulse width, period and duty of the TC3 pin input are measured in this mode, which can be used
in
decoding
the
remote
control
signals,
etc.
The
counter
is
free
running
by
the
internal
clock.
On
the
rising
(falling)
edge
of
the
TC3
pin
input,
the
current
contents
of
counter
is
loaded
into
TREG3A,
then
the
up-counter
is
cleared
and
an
INTTC3
interrupt
is
generated.
On
the
falling
(rising)
edge
of
the
TC3
pin
input,
the
current
contents
of
the
counter
is
loaded
into
the
TREG3B.
In
this
case,
counting
continues.
At
the
next
rising
(falling)
edge
of
the
TC3
pin
input,
the
current
contents
of
counter
are
loaded
into
TREG3A,
then
the
counter
is
cleared
again
and
an
interrupt
is
generated.
If
the
counter
overflows
before
the
edge
is
detected,
FF
h
issettotheTREG3Aand
an
overflow
interrupt
(INTTC3)
is
generated.
During
interrupt
processing,
it
can
be
determined
whether
or
not
there
is
an
overflow
by
checking
whether
or
not
the
TREG3A
value
is
FF
h
.
Also,
after
an
interrupt
(capture
to
TREG3A,
or
overflow
detection)
is
generated,
capture
and
overflow
detection
are
halted
until
TREG3A
has
been
read out; however, the counter continues.
After
TREG3A
has
been
read
out,
capture
and
overflow
detection
are
resumed,
usually,
TREG3B
is
read out first.
Internal clock
Up-counter
TC3 pin input
TREG3A
TREG3B
INTTC3 interrupt
Reading TREG3A
Ш1ЛЛДДЛЛДДЛЛЛЛДДЛЛЛЛГ
я
я
я
Figure 2-28. Timing Chart for Capture Mode (INT3ES = 0)
3
-
24-78
2002
-
10-03