4 divider output (dvo), Toshiba – Toshiba TMP87CP24AF User Manual
Page 63
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TOSHIBA
TMP87CM24A/P24A
Table 2-1. Time Base Timer Interrupt Frequency
TBTCK
NORMAL1/2, DLE1/2mode
SLOW, SLEEP mode
Interrupt Frequency
DV7CK = 0
DV7CK= 1
Atfc = 8MHz
At fs = 32.768 kHz
000
fc/223
fs/2^5
fs
/ 2
0.95 Hz
1 Hz
001
fc/2^''
fs/2^3
fs/2^3
3.81
4
010
fc/2^^
fs/2S
-
122.07
128
oil
fc/2'^
fs/2^
-
488.28
512
100
fc/2^3
fs/25
-
976.56
1024
101
fc/2^2
fs/2^
-
1953.12
2048
110
fc/2"
fs/23
-
3906.25
4096
111
fc/29
fs/2
-
15625
16384
2.4
Divider Output (DVO)
A
50%
duty
pulse
can
be
output
using
the
divider
output
circuit,
which
is
useful
for
piezo-electric
buzzer
drive. Divider output is from pin P13 (DVO). The P13 output latch should be set to "1" and then the P13
should be configured as an output mode.
Divider output circuit is controlled by the control register (TBTCR) shown in Figure 2-12.
TBTCR
(0036
h
)
7
6 5
4
3
2 1 0
DVOEN
DVpCK
(DV7CK)
(TBTEN)
,(TBTCK),
(Initial value : 0**0 0***)
DVOEN
Divider output enable/disable
0
1
Disable
Enable
00 : fc/2^3 or fs/2^[Hz]
R/W
D\/nrK
Divider output (DVO)
01
: fc/2^2 or fs/2'^
frequency selection
10 : fc/2" or fs/2^
11
: fc/2^° or fs/22
Note: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care
Figure 2-12. Divider Output Control Register
Example : 1 kHz pulse output (at fc =
8
MHz)
SET
(P1).3
; PI 3 output latch <-1
LD
(PI CR), 00001OOOB
; Configures PI 3 as an output mode
LD
(TBTCR), 10000000B
; DVOEN<-1, DVOCK<-00
Table 2-2. Frequency of Divider Output
DVOCK
Frequency of
Divider Output
At fc = 4.194304 MHz
Atfc = 8MHz
At fs = 32.768 kHz
00
fc/2’^
or
fs/2=
0.512 [kHz]
0.976 [kHz]
1.024 [kHz]
01
fc/2’2
fs/2^
1.024
1.953
2.048
10
fc/2"
fs/2^
2.048
3.906
4.096
11
fc/2’°
fs/2^
4.096
7.812
8.192
3
-
24-63
2002
-
10-03