3 function, Toshiba – Toshiba TMP87CP24AF User Manual
Page 80
Attention! The text in this document has been recognized automatically. To view the original document, you can use the "Original mode".
TOSHIBA
TMP87CM24A/P24A
2.8.3 Function
TC5 has 3 operating modes : timer, programmable divider output, and pulse width modulation output
mode.
(1)
Timer mode
In
this mode, the
internal clock is used for
counting up. The contents
of the
timer register 5 (TREG5)
is
compared
with
the
contents
of
the
up-counter.
Matching
with
TREG5
generates
a
timer/counter
5
interrupt (INTTC5) and clears the counter. Counting up resumes after the counter is cleared.
Table 2-6. Source Clock (Internal clock) for TC5
Source clock
resolution
maximum setting time
NORMAL1/2, DLE1/2mode
SLOW, SLEEP mode
fc = 8MHz
fs = 32.768
fc = 8MHz
fs = 32.768
DV7CK = 0
DV7CK= 1
kHz
kHz
fc/2" [Hz]
fs/2^ [Hz]
fs/2^ [Hz]
256 [//s]
244.14 [//s]
65.3 [ms]
62.3 [ms]
fc/2'
fc/2'
-
16
[/.S]
-
4.1 [ms]
-
fc/2^
fc/2^
-
1
[//S]
-
255 [//s]
-
(2)
Programmable divider output (PDO) mode
The
internal
clock
is
used
for
counting
up.
The
contents
of
the
TREG5
are
compared
with
the
contents
of
the
up-counter.
The
timer
F/F5
output
is
toggled
and
the
counter
is
cleared
each
time
a
match
is
found.
The
timer
F/F5
output
is
inverted
and
output
to
the
PDO
(P41)
pin.
In
the
case
of
PDO
output,
set
the
P41
output
latch
to
"1"
and
configure
as
an
output
with
P4CR1.
This
mode
can
be
used
for
50%
duty
pulse
output.
INTTC5
interrupt
is
generated
each
time
the
PDO
output
is
toggled.
Example 1024 Hz pulse output (atfc = 4.194304 MHz)
SET
(P4).1
P41 output latch<-1
LD
(TC5CR), 0000101 OB
Sets to TC5 modes and source clock
LD
(TREG5), 10H
1/1024^27fc^2 = IO
h
LD
(TC5CR), 0010101 OB
Starts TC5
Internal clock
PDOO pin
INTTC5 interrupt
Figure 2-31. PDO Mode Timing Chart
3
-
24-80
2002
-
10-03