Toshiba TMP87CP24AF - Manual (Page 48)

TOSHIBA
TMP87CM24A/P24A
Note: The watchdog timer consists of an internal divider and a two-stage binary counter. When
clear code 4E h is written, only the binary counter is cleared, not the internal divider.
Depending on the timing at which clear code 4E h is written on the WDTCR2 register, the
overflow time of the binary counter may be at minimum 314 of the time set in WDTCR1
<WDTT>. Thus, write the clear code using a shorter cycle than 314 of the time set in WDTCR1
<WDTT>.
Example : Sets the watchdog timer detection time to 22i/fc [s] and resets the CPU malfunction.
Within 3/4 of WDT
detection time
Within 3/4 of WDT
detection time
LD
r LD
^ LD
L LD
(WDTCR1), 00001101B
(WDTCR2), 4EH
(WDTCR2), 4EH
(WDTCR2), 4EH
WDTT<-10, WDTOUT<-1
Clears the binary counters
(always clear immediately after changing WDTT)
Clears the binary counters
Clears the binary counters
Watchdog Timer Control Register 1
7 6 5 4 3
WDTCR1
(0034 h )
WDT
EN
WCjJJ WDT
OUT
(Initial value 10 0 1 )
WDTEN
Watchdog timer
enable/disable 0
1 Disable (it is necessary to write the disable code to WDTCR2)
Enable
0 0 2 ^Vfc or 2'yfs [s]
Watchdog timer 0 1 2 ^Vfc or 2 ’Vfs
Write
WDTT
detection time 10 2 ^Vfc or 2 ’Vfs
only
11 2’7fc or 2 "/fs
WDTOUT
Watchdog timer 0 Interrupt request
output select 1 Reset output
Note 1: WDTOUT cannot be set to "1" by program after clearing WDTOUT to "0
Note 2: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz] *: Don't care
Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions.
Note 4: The watchdog timer must be disabled or the counter must be cleared immediately before entering
to the STOP mode. When the counter is cleared, the counter must be cleared again immediately
after releasing the STOP mode.
Watchdog Timer Control Register 2
7 6 5 4 3
WDTCR2
(0035 h )
(Initial value : **** ****)
WDTCR2
Watchdog timer control
code write register
4E h
BI h
others
Watchdog timer binary counter clear (clear code)
Watchdog timer disable (disable code)
Invalid
Write
only
Note 1: The disable code is invalid unless written when WDTEN = 0.
Note 2: *: Don't care
Note 3: Since WDTCR2 is a write-only register, read-modify-write instructions (e.g., bit manipulating
instructions such as SET or CLR and arithmetic instructions such as AND or OR) cannot be used for
read/write to this register.
Note 4: Write clear code 4E h within 3/4 of the time set in WDTCR1<WDTT>.
Figure 1-28. Watchdog Timer Control Registers
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24-48 2002
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10-03