Toshiba TMP87CP24AF - Manual (Page 36)

TOSHIBA
TMP87CM24A/P24A
SP
General-purpose register save/restore using push and pop instructions:
To save only a specific register, and when the same interrupt source occurs more than once,
the general-purpose registers can be saved/restored using push/pop instructions.
Example
PINTxx
Register save using push and pop instructions
PC l
PC.
PSW
At acceptance
of an interrupt
PUSH WA
PUSH HL
; interrupt processing
POP HL
POP WA
RETI
SP
L
H
A
W
PC l '
PC
PSW
At execution
of a push
instruction
SP
Save WA register pair
Save HL register pair
Restore HL register pair
Restore WA register pair
Return
PC l
PC.
PSW SP
At execution
of a pop
instruction
Address (example)
0238 h
0239
023A
023B
023C
023D
023E
023F
At execution of an
interrupt return
instruction
General-purpose registers save/restore using data transfer instruction:
Data transfer instructions can be used to save only a specific general-purpose register during
processing of a single interrupt.
Example : Saving/restoring a register using data transfer instructions
PINTxx: LD (GSAVA), A ; Save A register
interrupt processing ;
A, (GSAVA) ; Restore A register LD
RETI Return
The interrupt return instructions [RETI]/[RETN] perform the following operations.
[RETI] Maskable interrupt return
® The contents of the program counter and the
program status word are restored from the
stack.
® The stack pointer is incremented 3 times.
® The interrupt master enable flag is set to "1
[RETN] Non-maskable interrupt return
® The contents of the program counter and
program status word are restored from the
stack.
® The stack pointer is incremented 3 times.
® The interrupt master enable flag is set to "1"
only when a non-maskable interrupt is
accepted in interrupt enable status. However,
the interrupt master enable flag remains at " 0 "
when so clear by an interrupt service program.
Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next
interrupt can be accepted immediately after the interrupt return instruction is executed.
Note: When the interrupt processing time is longer than the interrupt request generation
time, the interrupt service task is performed but not the main task.
3
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24-36 2002
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10-03