1 external reset input, 2 address-trap-reset, 3 watchdog timer reset – Toshiba TMP87CP24AF User Manual
Page 51: 4 system-clock-reset, Toshiba
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TOSHIBA
TMP87CM24A/P24A
1.11.1
External Reset Input
When
the
RESET
pin
is
held
at
low
for
at
least
3
machine
cycles
(
1 2
/fc
[s])
with
the
power
supply
voltage
within
the
operating
voltage
range
and
oscillation
stable,
a
reset
is
applied
and
the
internal
state is initialized.
When
the
RESET
pin
input
goes
high,
the
reset
operation
is
released
and
the
program
execution
starts
at
the
vector
address
stored
at
addresses
FFFE
h
to
FFFF
h
^__
The
RESET
pin
contains
a
Schmitt
trigger
(hysteresis)
with
an
internal
pull-up
resistor.
A
simple
power-on-
reset
can
be
applied
by
connecting
an
external
capacitor and a diode.
Figure 1-30. Simple Power-on-
Reset Circuitry
1.11.2
Address-Trap-Reset
An
address-trap-reset
is
one
of
fail-safe
function
that
detects
CPU
malfunction
such
as
endless
looping
caused
by
noise
or
the
like,
and
returns
the
CPU
to
the
normal
state.
If
the
CPU
attempts
to
fetch
an
instruction
from
a
part
of
RAM
or
SFRs
(address
OOOO
h
to
083F
h
forTMP87CM24A/P24A),
an
address-trap-
reset will be generated. Then, the RESET pin output will go low. The reset time is 220/fc [s] (131 ms at
8
MHz).
Execution
Z)C
JP
Reset
Reset release
Xlristruction at address r
RESET output
r Address-trap is occurred
1________ ("L" output) ((
|(High-Z)|
22“/fc [s]
2Vfc
to
2^/fc
2^/fc
Hotel:
0^a^083FH
Note 2:
During reset release, reset vector "r" is read out, and an instruction at address r is fetched and decoded.
Figure 1-31. Address-Trap-Reset
1.11.3
Watchdog Timer Reset
Refer to Section "1.10 Watchdog Timer".
1.11.4
System-Clock-Reset
Clearing
both
XEN
and
XTEN
(bits
7
and
6
in
SYSCR2)
to
"0"
stops
both
high-frequency
and
low-
frequency
oscillation,
and
causes
the
MCU
to
deadlock.
This
can
be
prevented
by
automatically
generating
a
reset
signal
whenever
XEN
=
XTEN
=
0
is
detected
to
continue
the
oscillation.
Then,
the
RESET pin output goes low from high-impedance. The reset time is
220/fc
[s] (131 ms at
8
MHz).
3
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24-51
2002
-
10-03