3 watchdog timer interrupt (intwdt), Toshiba – Toshiba TMP87CP24AF User Manual
Page 49
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TOSHIBA
TMP87CM24A/P24A
Table 1-4. Watchdog Timer Detection Time
Operating mode
Detection time
NORMAL1
NORMAL2
SLOW
Atfc =
8
MHz
At fs = 32.768 kHz
2
^Vfc [s]
2
^Vfc, 2’7fs
rVh
4.194 s
4s
2
^Vfc
2
^Vfc,
2
’Vfs
2
’Vfs
1.048 ms
1
s
2
'Vfc
2
^Vfc,
2
’Vfs
—
262.1 ms
250 ms
2’7fc
2’7fc,
2
"/fs
—
65.5 ms
62.5 ms
(2)
Watchdog Timer Enable
The
watchdog
timer
is
enabled
by
setting
WDTEN
(bit
3
in
WDTCR1)
to
" 1 W D T E N
is
initialized
to
"
1
" during reset, so the watchdog timer operates immediately after reset is released.
Example: Enables watchdog timer
LD
(WDTCR1), 00001OOOB
; WDTEN<-1
(3)
Watchdog Timer Disable
The
watchdog
timer
is
disabled
by
writing
the
disable
code
(B1
h
)
to
WDTCR2
after
clearing
WDTEN
(bit
3
in
WDTCR1)
to
"0".
The
watchdog
timer
is
not
disabled
if
this
procedure
is
reversed
and
the
disable code is written to WDTCR2 before WDTEN is cleared to "0".
During disabling the watchdog timer, the binary counters are cleared to "0".
Example: Disables watchdog timer
LDW (WDTCR1), 0B101H
; WDTEN<-0,WDTCR1<-disable code
1.10.3
Watchdog Timer Interrupt (INTWDT)
This
is
a
pseudo
non-maskable
interrupt
which
can
be
accepted
regardless
of
the
contents
of
the
EIR.
If
a
watchdog
timer
interrupt
or
a
software
interrupt
is
already
accepted,
however,
the
new
watchdog
timer
interrupt
waits
until
the
previous
interrupt
processing
is
completed
(the
end
of
the
[RETN]
instruction
execution).
The
stack
pointer
(SP)
should
be
initialized
before
using
the
watchdog
timer
output
as
an
interrupt
source with WDTOUT.
Example : Watchdog timer interrupt setting up.
LD
SP, 083FH
;
LD
(WDTCR1), 00001 OOOB ;
Sets the stack poi nter
WDTOUT<-0
3
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24-49
2002
-
10-03