Toshiba TMP87CP24AF - Manual (Page 74)

TOSHIBA
TMP87CM24A/P24A
2.6 16-Bit Timer/Counter 2 (TC2)
2.6.1 Configuration
INTTC2
interrupt
Timer/Counter 2 control register 16-bit timer register 2 TREG2H TREG2L
write strobe write strobe
Figure 2-23. Timer/Counter 2 (TC2)
2.6.2 Control
Thetimer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register
2 (TREG2). Reset does not affect TREG2.
TREG2
(0016, 001 7 h )
TC2CR
(0015 h )
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
_____ ^^________ T,REG2 h ,(0017 h )___^^_________ _____ ^^________ T’^EG2 l ,(0016 h )__ ^^_________
7 6 5 4 3 2 1 0
write only
TC2S TC2CK, TC2M (Initial value : **00 00*0)
TC2M
Timer/counter 2 operating 0 Timer/Event counter mode
mode select 1 Window mode
000 Internal clock fc/2^^ or fs/2’=[Hz]
001 Internal clock fc/2’3 or fs/2=
010 Internal clock fc/2»
TC2CK Timer/counter 2 oil Internal clock fc/2^ Write
source clock select 100 Internal clock fc (Note 5) only
101 Internal clock fs
110 Reserved
111 External clock (TC2 pin input)
TC2S
Timer/counter 2 0 Stop and counter clear
start control 1 Start
Notel: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care
Note 2: When writing to the low-byte of timer register 2 (TREG2i), the comparison is inhibited until
the high-byte (TREG2 h ) is written.
After writing to the high-byte, any match during 1 machine cycle (instruction execution
cycle) is ignored.
Note 3: Set the mode and source clock when timer/counter stops (TC2S = 0).
Note 4: Values to be loaded to the timer register must satisfy the following condition.
TREG2 > 0(TREG2isfoii>0 when warm-up).
Note 5: "fc" can be selected as the source clock only in the timer mode during the SLOW mode.
Note 6: TC2CR and TREG2 are write-only registers and must not be used with any of the read-
modify-write instructions.
Figure 2-24. Timer Register 2 and TC2 Control Register
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24-74 2002
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10-03