Altera Nios Development Board - Manual (Page 11)

Altera Corporation 1–3
July 2005 Nios Development Board Reference Manual, Stratix II Edition
Introduction
Factory-
Programmed
Reference
Design When power is applied to the board, on-board logic configures the
Stratix II FPGA using hardware configuration data stored in flash
memory. When the device is configured, the Nios II processor design in
the FPGA wakes up and begins executing boot code from flash memory.
The board is factory-programmed with a default reference design. This
reference design is a web server that delivers web pages via the Ethernet
port. For further information on the default reference design, see
Appendix C, Connecting to the Board via Ethernet .
In the course of development, you may overwrite or erase the flash
memory space containing the default reference design. Altera provides
the flash image for the default reference design so you can return the
board to its default state. See
Appendix B, Restoring the Factory
Configuration for more information.