Altera Nios Development Board - Manual (Page 39)

Altera Corporation 2–31
July 2005 Nios Development Board Reference Manual, Stratix II Edition
Board Components
Figure 2–17. Reset, Config Button
JTAG
Connectors (J24
& J5) The Nios development board, has two 10-pin JTAG headers (J24 and J5)
compatible with Altera download cables, such as the USB-Blaster
™ . Each
JTAG header connects to one Altera device and forms a single-device
JTAG chain. J24 connects to the Stratix II device (U60), and J5 connects to
the EPM7128AE device (U3).
JTAG Connector to Stratix II Device (J24)
J24 connects to the JTAG pins (TCK, TDI, TDO, TMS, TRST) of the
Stratix II device (U60) as shown in
Figure 2–18 . Altera Quartus II
software can directly configure the Stratix II device with a new hardware
image via an Altera download cable as shown in
Figure 2–19 . In addition,
the Nios II IDE can access the Nios II processor JTAG debug module via
a download cable connected to the J24 JTAG connector.
Figure 2–18. JTAG Connector (J24) to Stratix II Device