Altera Nios Development Board - Manual (Page 43)

Altera Corporation 2–35
July 2005 Nios Development Board Reference Manual, Stratix II Edition
Board Components
■ Drive the PROTO1 & PROTO2 connectors via pin A12, driven by on-
chip PLL5.
■ Feedback to FPGA pin N2 (CLK11p). This clock feedback path is not
used by Altera-provided reference designs, but is available to the
user if necessary.
The 50 MHz oscillator (Y2) is socketed and can be changed or removed by
the user. To drive the clock circuitry using the external clock connector
(J4), you must first stuff location R15 with a 49.9 ohm 0603 resistor and
stuff location R13 with a 330 ohm 0603 resistor. Note that the
configuration controller and other Altera-provided reference designs are
designed to work only with the 50 MHz clock. If you change the clock
frequency, it is your responsibility to accommodate the new clock
everywhere it is used on the development board.
Power-Supply
Circuitry The Nios development board runs from a 17V, unregulated, input power
supply. On-board circuitry generates 5V, 3.3V, and 1.2V regulated power
levels.
■ The input power-supply can be either center-negative or center-
positive. A bridge rectifier (D34) presents the appropriate polarity to
the voltage regulators.
■ The 5V supply is presented on pin 2 of J12 and J15 for use by any
device plugged into the PROTO1 & PROTO2 expansion connectors.
■ The 3.3V supply is used as the power source for all Stratix II device
I/O pins. The 3.3V supply is also available for PROTO1 & PROTO2
daughter cards.
■ The 1.2V supply is used only as the power supply for the Stratix II
device core (VCCINT) and it is not available on any connector or
header.