Altera Nios Development Board - Manual (Page 19)

Altera Corporation 2–11
July 2005 Nios Development Board Reference Manual, Stratix II Edition
Board Components
f
Refer to www.idt.com for detailed information about the SRAM devices.
Flash Memory
(U5) U5 is a 16 Mbyte AMD AM29LV128M flash memory device connected to
the Stratix II device and can be used for two purposes:
1. A Nios II embedded processor implemented on the Stratix II device
can use the flash as general-purpose readable memory and non-
volatile storage.
2. The flash memory can hold Stratix II device configuration data that
is used by the configuration controller to load the Stratix II device at
power-up. See
“Configuration Controller Device (U3)” on page 2–25
for related information.
A Nios II processor design in the FPGA can identify the 16 Mbyte flash
memory in its address space, and can program new data (either new
Stratix II configuration data, Nios II embedded processor software, or
both) into flash memory. The Nios II embedded processor software
includes subroutines for writing and erasing flash memory.
The flash memory device shares address and data connections with the
SRAM chips and the Ethernet MAC/PHY chip. For shared bus
information, see
Appendix A, Shared Bus Table .
The on-board configuration controller makes assumptions about what-
resides-where in flash memory. For details see section
“Flash Memory
Partitions” on page 2–27 .
f
See www.amd.com for detailed information about the flash memory
device.