Altera Nios Development Board - Manual (Page 33)

Altera Corporation 2–25
July 2005 Nios Development Board Reference Manual, Stratix II Edition
Board Components
Configuration
Controller
Device (U3) The configuration controller (U3), is an Altera MAX ® 7000 EPM7128AE
device. It comes preprogrammed with logic for managing board reset
conditions and configuring the Stratix II device from data stored in flash
memory.
Reset Distribution
The EPM7128AE device takes a power-on reset pulse from the Linear
Technologies 1326 power-sense/reset-generator chip and distributes it
(through internal logic) to other reset pins on the board, including the:
■ LAN91C111 (Ethernet MAC/PHY) reset
■ Flash memory reset
■ CompactFlash reset
■ Reset signals delivered to the expansion prototype connectors
(PROTO1 & PROTO2)
Starting Configuration
There are four methods to start a configuration sequence. The four
methods are the following:
1. Board power-on.
2. Pressing the Reset, Config button (SW10).
3. Asserting (driving 0 volts on) the EPM7128AE's reconfigreq_n
input pin (from a Stratix II design).
4. Pressing the Factory Config button (SW9).
Stratix II Configuration
At power-up or reset, the configuration controller reads data out of the
flash memory, and presents the necessary control signals to configure the
Stratix II device. The Stratix II device is configured using fast passive
parallel mode.
f
For detailed information about the Altera EPM7128AE device, refer to
the MAX 7000 family literature at www.altera.com/literature/lit-
m7k.html
.
FPGA configuration data files are generated by the Quartus II software.
You can write new configuration data to the board's flash memory using
the Nios II integrated development environment (IDE).