Document Outline

• Table of Contents
• Introduction
  • Introduction
  • Audience
  • Product Overview
  • Free Topology Technology Overview
  • Related Documentation
• Hardware Resources
  • Overview
  • Neuron Processor Architecture
  • Memory Allocation
    • FT 3120 Smart Transceiver
    • FT 3150 Smart Transceiver
    • EEPROM
    • Static RAM
    • Preprogrammed ROM
    • External Memory of the FT 3150 Smart Transceiver
  • Input/Output
    • Eleven Bidirectional I/O Pins
    • Two 16-Bit Timer/Counters
  • Clock Input
    • Clock Generation
  • Additional Functions
    • Reset Function
    • RESET Pin
      • Power Up Sequence
      • Software Controlled Reset
      • Watchdog Timer
      • LVI Considerations
    • Reset Processes and Timing
    • SERVICE Pin
  • Integrity Mechanisms
    • Memory Integrity Using Checksums
    • Reboot and Integrity Options Word
    • Reset Processing
    • Signatures
• Input/Output Interfaces
  • Overview
  • Hardware Considerations
  • I/O Timing Issues
    • Scheduler-Related I/O Timing Information
    • Firmware and Hardware-Related I/O Timing Information
  • Direct I/O Objects
    • Bit Input/Output
    • Byte Input/Output
    • Leveldetect Input
    • Nibble Input/Output
  • Parallel I/O Objects
    • Muxbus Input/Output
    • Parallel Input/Output
      • Master/Slave A Mode
      • Slave B Mode
      • Token Passing
      • Handshaking
      • Data Transferring
  • Serial I/O Objects
    • Bitshift Input/Output
    • I2C Input/Output
    • Magcard Input
    • Magtrack1 Input
    • Neurowire (SPI Interface) Input/Output Object
      • Neurowire Master Mode
      • Neurowire Slave Mode
    • Serial Input/Output
    • Touch Input/Output
    • Wiegand Input
  • Timer/Counter Input Objects
    • Dualslope Input
    • Edgelog Input
    • Infrared Input
    • Ontime Input
    • Period Input
    • Pulsecount Input
    • Quadrature Input
    • Totalcount Input
  • Timer/Counter Output Objects
    • Edgedivide Output
    • Frequency Output
    • Oneshot Output
    • Pulsecount Output
    • Pulsewidth Output
    • Triac Output
    • Triggered Count Output
  • Notes
• Hardware Design Considerations
  • Introduction
  • Quick Start for Users Familiar with the FTT-10A Transceiver
  • Interface between Smart Transceivers and the Network
  • PC Board Layout Guidelines
  • EMI Design Issues
  • ESD Design Issues
  • Lightning Protection
    • Building Entrance Protection
    • Network Line Protection
    • Shield Protection
    • Suggested Gas Discharge Arresters
  • EN 61000-4 Electromagnetic Compatibility (EMC) Testing
• Network Cabling and Connections
  • Network Connection
  • Network Topology Overview
  • System Performance and Cable Selection
    • System Specifications
    • Transmission Specifications
  • Cable Termination and Shield Grounding
    • Free Topology Network Segment
    • Doubly Terminated Bus Topology Segment
    • Grounding Shielded Twisted Pair Cable
• Programming Considerations
  • Application Program Development and Export
  • NodeBuilder Development Tool
    • Development Hardware Setup
    • Release Hardware Setup
• FT Smart Transceiver Design Checklist
  • Introduction
  • Device Checklist
• Qualified TP/FT-10 Cable Specifications and Sources
  • Introduction
  • Qualified Cables
    • Category 5 Cable Specifications
    • NEMA Level IV Cable Specifications
    • 16AWG/1.3mm “Generic” Cable Specifications
• Design and Handling Guidelines
  • Application Considerations
    • Termination of Unused Pins
    • Avoidance of Damaging Conditions
    • Power Supply, Ground, and Noise Considerations
    • Decoupling Capacitors
  • Board Soldering Considerations
    • Soldering Through-hole Parts (FT-X1)
    • Soldering Surface Mount (SMT) Parts (Free Topology Transceivers)
  • Handling Precautions and Electrostatic Discharge
    • Electrostatic Discharge
    • Recommended Reading
  • Power Distribution and Decoupling Capacitors
  • Recommended Bypass Capacitor Placement
• Reference Design Schematics and Layout
  • Mini Evaluation Kit Board
  • FT 3150 Evaluation Board Core
  • FT 3150 Evaluation Board Peripheral Circuitry
  • FT 3150 Evaluation Board Composite Top Layer
  • FT 3150 Evaluation Board Top Layer
  • FT 3150 Evaluation Board Internal Ground Layer
  • FT 3150 Evaluation Board Internal Power Layer
  • FT 3150 Evaluation Board Bottom Layer
  • FT 3150 Evaluation Board Composite Bottom Layer