Echelon FT 3150 Smart Transceiver - Manual (Page 137)

FT 3120 / FT 3150 Smart Transceiver Data Book 131
Application Considerations
• Bypass capacitors should be connected between the V
DD
and V
SS
pairs with minimal trace length. These
capacitors help supply the instantaneous currents of the digital circuitry in addition to decoupling the
noise that may be generated by other sections of the device or other circuitry on the power supply.
• Use short, wide, low-inductance traces to connect all of the V
SS
ground pins together. Depending on the
application, a double-sided PCB with a V
SS
ground plane under the device connecting all of the digital
and analog V
SS
pins together would be a good grounding method. A multilayer PCB with a ground plane
connecting all of the digital and analog V
SS
pins together would be the optimal ground configuration.
These methods will result in the lowest resistance and the lowest inductance in the ground circuit. This is
important to reduce voltage spikes in the ground circuit resulting from the high-speed digital current
spikes. Suppressing these voltage spikes on the integrated circuit is the reason for multiple V
SS
ground
leads.
• Use short, wide, low-inductance traces to connect all of the V
DD
power supply pins together. Depending on
the application, a double-sided PCB with V
DD
bypass capacitors to the V
SS
ground plane under the device
may complete the low-impedance coupling for the power supply. For a multilayer PCB with a power plane,
connecting all of the digital and analog V
DD
pins to the power plane would be the optimal power distribution
method. The integrated circuit layout and packaging considerations for the 5V V
DD
power circuit are essen-
tially the same as for the ground circuit.
Decoupling Capacitors
The switching waveforms shown in Figures C.4 and C.5 show the current spikes introduced to the power supply and
ground lines. This effect is shown for a load capacitance of less than 5pF or for 50pF. For ideal power supply lines
with no series impedance, the spikes would pose no problem. However, actual power supply and ground lines do
possess series impedance, giving rise to noise problems. For this reason, care should be taken in board layouts,
ensuring low-impedance paths to and from logic devices.
To absorb switching spikes, the following CMOS devices should be bypassed with good quality 0.022µF to 0.33µF
decoupling capacitors:
• Bypass every device driving a bus with all outputs switching simultaneously.
• Bypass all synchronous counters.
• Bypass devices used as oscillator elements.
• Bypass Schmitt-trigger devices with slow input rise and fall times. The slower the rise and fall time, the
larger the bypass capacitor. Lab experimentation is suggested.
Bypass capacitors should be distributed over the circuit board. In addition, boards could be decoupled with a 1 µF
capacitor.