Echelon FT 3150 Smart Transceiver - Manual (Page 55)

FT 3120 / FT 3150 Smart Transceiver Data Book 49
Parallel I/O Objects
Notes:
1. Refer to the FT 3120 and FT 3150 Smart Transceiver Datasheet for detailed measurement information.
2. For FT Smart Transceiver-to-FT Smart Transceiver operation, bus contention (t
mrdz
, t
sawdd
) is eliminated by firmware, ensuring that a zero state
is present when the token is passed between the master and slave. See Parallel I/O Interface to the Neuron Chip engineering bulletin for further
information.
3. If t
sarwh
< 150 ns, then t
sawdh
= t
sarwh
.
5. CLK1 represents the period of the FT Smart Transceiver input clock (100 ns at 10MHz).
6. In slave A mode, the HS signal is high a minimum of 4 CLK1 periods. The typical time HS is high during consecutive data reads or consecutive
data writes is also 4 CLK1 periods.
Figure 3.18 Slave A Mode Timing
The following is a pair of example programs that transfer data in a parallel I/O master/slave A configuration. The
code is for two LonBuilder emulators hardwired as shown in Figure 3.16. The master program writes the test_data to
the input bufferof the slave (as the master owns the token after reset and has the first option to write on the bus) and
the slave then outputs data to the input buffer of the master. The buffers can be viewed through the LonBuilder
debugger to verify the transfer was complete. The master transmits [5,1,1,1,1,1] to the slave and the slave transmits
[7,1,2,3,4,5,6,7,0,0,0,0,0,0] to the master. The first byte indicates the number of bytes being passed; the following
non-zero valued bytes in this example are the actual data transferred. The remaining length of the array, if any, is
Symbol Description Min Typ Max
t
sarws
R/W setup before falling edge of CS 25 ns — —
t
sarwh
R/W hold after rising edge of CS 0 ns — —
t
sacspw
CS pulse width 45 ns — —
t
sahsh
HS hold after rising edge of CS 0 ns — —
t
sahsv
HS valid after rising edge of CS — — 50 ns
t
sawdd
Slave A drive of DATA after rising edge of R/W (Notes 1, 2) 0 ns 5 ns —
t
sawds
Write data valid before falling edge of HS 150 ns 2 CLK1 —
t
sawdh
Write data valid after rising edge of CS 150 ns
(Note 3)
2 CLK1 —
t
sardz
Slave A three-state DATA after falling edge of R/W (Note 1) — — 50 ns
t
sards
Read data setup before rising edge of CS 25 ns — —
t
sardh
Read data hold after rising edge of CS 10 ns — —
CS
HS
R/W
DATA OUT
DATA IN
READ CYCLE
(MASTER WRITE)
WRITE CYCLE
(MASTER READ)
t
sawdh
t
sahsv
t
sacspw
t
sacspw
t
sahsv
t
sarws
t
sarws
t
sards
t
sardh
t
sawd
t
sardz
t
sarwh
t
sahsh
t
sahsh
t
sawds