Echelon FT 3150 Smart Transceiver - Manual (Page 53)

FT 3120 / FT 3150 Smart Transceiver Data Book 47
Parallel I/O Objects
the slave B configuration, with the other microprocessor as the master. Handshaking is used in both modes to control
the instruction execution, and application processing is suspended for the duration of the transfer (up to 255 bytes/
transfer). Consult the Neuron C Reference Guide for detailed programming instructions.
Upon a reset condition, the master processor monitors the low transition of the handshake (HS) line from the slave,
then passes a CMD_RESYNC (0x5A) for synchronization purposes. This must be done within 0.84 seconds after
reset goes high with a FT Smart Transceiver slave running at 10MHz, to avoid a watchdog reset error condition (see
the Neuron C Programmer’s Guide). The CMD_RESYNC is followed by the slave acknowledging with a
CMD_ACKSYNC (0x07). This synchronization ensures that both processors are properly reset before data transfer
occurs. When interfacing two FT Smart Transceivers, these characters are passed automatically (refer to the flow
table illustrated later in this section). However, when using parallel I/O to interface the FT Smart Transceiver to
another microprocessor, that microprocessor must duplicate the interface signals and characters that are automatically
generated by the parallel I/O function of the FT Smart Transceiver.
For additional information, see the Parallel I/O Interface to the Neuron Chip engineering bulletin.
The timing numbers shown in this section are valid for both an explicit I/O call or an implicit I/O call through a when
clause, and are assumed to be for a FT Smart Transceiver running at 10MHz.
Master/Slave A Mode
This mode is recommended when interfacing two FT Smart Transceivers. In a master/slave A configuration, the
master drives IO8 as a chip select and IO9 to specify a read or write cycle, and the slave drives IO10 as a handshake
(HS) acknowledgment (see Figure 3.16). The maximum data transfer rate is 1 byte per 4 processor instruction cycles,
or 0.6 µs per byte at a 40MHz input clock rate. The data transfer rate scales proportionally to the input clock rate (a
master write is a slave read). Timing for the case where the FT Smart Transceiver is the master (Figure 3.17), refers to
measured output timing at 10MHz. After every byte write or byte read, the HS line is monitored by the master, to
verify the slave has completed processing (when HS = 0) and the slave is ready for the next byte transfer. This is done
automatically in FT Smart Transceiver-to-FT Smart Transceiver (master/slave A mode) data transfers. The HS line
should be pulled up (inactive) with a 10k resistor to ensure proper resynch behavior after the slave resets.
Slave A timing is shown in Figure 3.18.
Figure 3.16 Parallel I/O — Master and Slave A
Ω
PARALLEL SLAVE A PARALLEL MASTER
IO10
IO9
IO8
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
D0 – D7
HS
R/W
CS
IO10
IO9
IO8
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
D0 – D7
HS
R/W
CS