Echelon FT 3150 Smart Transceiver - Manual (Page 93)

FT 3120 / FT 3150 Smart Transceiver Data Book 87
Timer/Counter Output Objects
The hardware update does not happen until the occurrence of an external active sync clock edge. The internal timer is
then enabled and a triac gate pulse is generated after the user-defined period has elapsed. This sequence is repeated
indefinitely until another update is made to the triac gate pulse delay value.
t
fout
(min) refers to the delay from the initiation of the function call to the first sampling of the sync input. In
the absence of an active sync clock edge, the input is repeatedly sampled for 10ms (1/2 wave of a 50 Hz line
cycle time), t
fout
(max), during which the application processor is suspended.
The output gate pulse is gated by an internal clock with a constant period of 25.6µs (independent of the FT Smart
Transceiver input clock). Since the input trigger signal (zero crossing) is asynchronous relative to this internal
clock, there is a jitter, t
jit
, associated with the output gate pulse.
The actual active edge of the sync input and the triac gate output can be set by using the clock edge or invert
parameters, respectively.
Triggered Count Output
A timer/counter may be configured to generate an output pulse that is asserted under program control, and de-asserted
when a programmable number of input edges (up to 65,535) has been counted on an input pin (IO4 – IO7). Assertion
may be either logic high or logic low. This object is useful for controlling stepper motors or positioning actuators
which provide position feedback in the form of a pulse train. The drive to the external device is enabled until it has
moved the required distance, and then the device is disabled. See Figure 3.50.