Echelon FT 3150 Smart Transceiver - Manual (Page 3)

FT 3120 / 3150 Smart Tranceiver Data Book i
Table of Contents
Chapter 1 - Introduction ......................................................................................1
Introduction .......................................................................................................2
Audience ...........................................................................................................2
Product Overview .............................................................................................2
Free Topology Technology Overview ..............................................................4
Related Documentation .....................................................................................5
Chapter 2 - Hardware Resources ........................................................................7
Overview ...........................................................................................................8
Neuron Processor Architecture .........................................................................8
Memory Allocation .........................................................................................13
FT 3120 Smart Transceiver ......................................................................13
FT 3150 Smart Transceiver ......................................................................13
EEPROM ..................................................................................................14
Static RAM ...............................................................................................16
Preprogrammed ROM ...............................................................................16
External Memory of the FT 3150 Smart Transceiver ...............................16
Input/Output ...................................................................................................17
Eleven Bidirectional I/O Pins ...................................................................17
Two 16-Bit Timer/Counters ......................................................................17
Clock Input .....................................................................................................18
Clock Generation ......................................................................................18
Additional Functions .......................................................................................19
Reset Function ..........................................................................................19
RESET Pin ................................................................................................20
Power Up Sequence ............................................................................20
Software Controlled Reset ..................................................................21
Watchdog Timer .................................................................................21
LVI Considerations .............................................................................21
Reset Processes and Timing .....................................................................22
SERVICE Pin ...........................................................................................27
Integrity Mechanisms .....................................................................................28
Memory Integrity Using Checksums ........................................................28
Reboot and Integrity Options Word ..........................................................29
Reset Processing .......................................................................................30
Signatures ..................................................................................................30
Chapter 3 - Input/Output Interfaces ................................................................31
Overview .........................................................................................................32
Hardware Considerations ................................................................................33
I/O Timing Issues ............................................................................................37
Scheduler-Related I/O Timing Information ..............................................38
Firmware and Hardware-Related I/O Timing Information .......................39