Echelon FT 3150 Smart Transceiver - Manual (Page 135)

FT 3120 / FT 3150 Smart Transceiver Data Book 129
Application Considerations
The maximum peak temperature for the FT 3150 is 235ºC. For the FT 3120, the maximum peak temperature depends
upon the model: for the 32L it is 220ºC while the 44L is 235ºC. Consult the data sheet of the solder manufacture for
recommendations on the optimum reflow profile. The actual reflow profile you choose should consider these peak
temperature limitations.
Most potentially destructive AC waveforms fall into one of two categories. One type is high-voltage (10kV – 25kV),
low-energy spikes usually under 100ns in duration due to ESD discharge. ESD modeling has shown that the human
body can generate and discharge electrostatic voltages of up to 12kV. The second type is lower-voltage, higher-
energy transients that can last for several hundred microseconds or more and can be caused by capacitive coupling of
lightning or inductive load sources. Different protection devices must be implemented, depending on what is
anticipated in the operating environment. Failure modes can be quantified and protective precautions taken to avoid
product malfunction. This may be PC board layout-related or may involve the use of external protection devices. All
pins on the FT Smart Transceiver have internal diode protection that will protect ESD type transients up to 2.2kV.
External protection is required in products subject to human contact or where interfaces to other equipment may be
encountered.
Many factors, including ambient temperature and semiconductor lot-to-lot processing variations, will influence the
effect of illegal conditions on the FT Smart Transceiver. The V
SS
ground pins are internally connected to the substrate
of the silicon die and are the reference point for all voltages. The FT Smart Transceiver functions for a V
DD
connected to the positive supply pin(s). In limited temperature range environments, the device may operate over
a wider V
DD
with timing, drive, FT transceiver and other specifications not met. There may also be some adverse
effects on gate oxides from long-term exposures to V
DD
greater than 5.5V.
Zap and latch-up refer to two damage mechanisms resident in CMOS ICs. Zap refers to damage caused by very-
high-voltage, static-electricity exposure. This damage usually appears as breakdown of the relatively thin oxide
layers that causes leakage or shorts. Often secondary damage occurs after an initial zap failure causes a short.
Latch-up refers to a usually catastrophic condition that is caused by turning on a parasitic, bipolar, silicon-controlled
rectifier (SCR). A latch-up is formed by N and P regions in the layout of the integrated circuit, which act as the
collector, base, and emitter of parasitic transistors. Bulk resistance of silicon in the wells and substrate acts as
resistors in the SCR circuit. Application of voltages to pins above V
DD
+ 0.3V or below V
SS
– 0.3V in conjunction
with enough current to develop voltage drops across the parasitic resistors can cause the SCR to turn on. Once on,
the SCR can be turned off only by removal of all power and applied voltages. The low on-impedance of the SCR
circuit can overheat and destroy the IC.
Figure C.2 shows the MOS circuitry for a digital input-only pin. The gates of the input buffer are very high
impedance for all voltages that would ever be applied to the pin. Protection is implemented with a P-channel
transistor acting as a diode to V
DD
and an N-channel transistor acting as a diode to V
SS
. Allowing a pin to float or
be driven to a mid-supply level can result in both the N- and P-channel devices in the input buffer simultaneously
being partially on, which causes excess current and noise on the V
DD
/V
SS
power supply. If a digital input is
driven above V
DD
, the pseudo-diode will conduct, protecting the input. As the current is increased to high levels
(100mA), damage can result. Figure C.3 shows the CMOS circuitry for a digital input/output-only pin.