Echelon FT 3150 Smart Transceiver - Manual (Page 139)

FT 3120 / FT 3150 Smart Transceiver Data Book 133
Handling Precautions and Electrostatic Discharge
Soldering Surface Mount (SMT) Parts (Free Topology Transceivers)
Please refer to the table below for guidance on the maximum reflow temperature for surface mount (SMT) parts. In
all cases, consult the solder manufacturer’s datasheet for recommendations on optimum reflow profile. The actual
reflow profile chosen should consider the peak temperature limitations, listed below.
The FT Smart Transceivers have a Level 3 Classification in IPC/JEDEC Standard J-STD-020C. Surface mount
reflow is the recommended soldering technique for all FT Smart Transceivers. Soldering techniques that involve
immersing the entire part are not recommended. Consult the solder manufacturer’s datasheet for recommendations on
optimum reflow profile.
Dry pack is a process which slowly bakes moisture from the surface mount technology (SMT) package and then seals
it into a dry pack bag to shield the unit from moisture in the atmosphere. The exterior of the bag will be marked with
a label that indicates the devices are moisture sensitive and is marked with the date the bag was sealed (there is a one-
year shelf life for these devices). There is a limited amount of time to use surface-mount devices once they are
removed from the dry pack. Before surface mounting, packages should not be out of the dry pack longer than 168
hours at < 60% relative humidity and < 30°C. If the units have not been shipped dry pack or have been unpacked
for too long, then units must be baked at 125°C for 6 hours prior to board soldering. The old recommendation was
24 hours at 125°C. If this is not done, some percentage of the units will exhibit destructive failures or latent
failures after the soldering process.
Handling Precautions and Electrostatic Discharge
All CMOS devices have an insulated gate that is subject to voltage breakdown. The gate oxide for the FT Smart
Transceiver breaks down at a gate-source potential of about 10V. The high-impedance gates on the devices are
protected by on-chip networks. However, these on-chip networks do not make the IC immune to ESD. Laboratory
tests show that devices may fail after one very high voltage discharge. They may also fail due to the cumulative effect
of several discharges of lower potential.
Static-damaged devices behave in various ways, depending on the severity of the damage. The most severely
damaged are the easiest to detect because the input or output has been completely destroyed and is shorted to V
DD
,
shorted to V
SS
, or is open-circuited. As a result of this, the device will no longer function. Less severe cases are
more difficult to detect because they appear as intermittent failures or degraded performance. Static damage can
often increase leakage currents.
CMOS devices are not immune to large static voltage discharges that can be generated while handling. For example,
static voltages generated by a person walking across a waxed floor have been measured in the 4 kV – 15 kV range
(depending on humidity, surface conditions, etc.). Therefore, the following precautions should be observed.
1. Do not exceed the maximum ratings specified by the data sheet.
2. All unused device inputs should be connected to V
DD
or V
SS
.
Product RoHS Compatible Model Numbers Peak Temperature ( ºC)
FT 3120-E4S40 No 14210-500, 14211-500 220
FT 3120-E4P40 No 14220-800, 14221-800 235
FT 3150-P20 No 14230-450 235
FT 3120-E4S40 Yes 14212R-500 245
FT 3120-E4P40 Yes 14222R-800 260
FT 3150-P20 Yes 14230R-450 260