Intel 21555 - Manual (Page 110)

110 21555 Non-Transparent PCI-to-PCI Bridge User Manual
Error Handling
12.3 System Error (SERR#) Reporting
The 21555 has two system error pins. Signal p_serr_l reports system errors on the primary interface, and s_serr_l
reports system errors on the secondary interface. For the 21555 to assert the SERR# signal for that interface, the
SERR# Enable must be set in the Command Configuration register corresponding to that interface. In addition,
each device-specific condition has a disable bit for each interface. When a disable bit for a particular condition is
set, SERR# assertion is masked for that condition. SERR# may be asserted for any of the following conditions:
• Address parity error (disabled by the corresponding Parity Error Enable bit).
• Parity error reported on target bus only during a posted write transaction (disabled by the corresponding Parity
Error Enable bit).
• Target abort detected during posted write transaction.
Note: The Master Abort Mode Bit in the Chip Control register must be set in order for SERR to assert on
the following condition.
• Master abort detected during posted write transaction.
• Posted write discarded after 2
24
target retries received from target.
• Delayed write request discarded after 2
24
target retries received from target.
• Delayed read request discarded after 2
24
target retries received from target.
• Delayed transaction completion discarded after master timeout counter expired.
For the above conditions, SERR# is asserted on the interface corresponding to the location of the initiator of the
transaction.
When the SERR# Forward Enable bit in the Chip Control 0 configuration register is set, the 21555 asserts p_serr_l
when it detects s_serr_l asserted, including those cases where the 21555 has asserted s_serr_l.