Intel 21555 - Manual (Page 169)

21555 Non-Transparent PCI-to-PCI Bridge User Manual 169
List of Registers
Table 93. I2O Outbound Post_List Counter
Byte Offsets: 063:060h
Bit Name R/W Description
15:0 Outbound Post Ctr R/(WS)
When read, returns the number of entries in the Outbound
Post_List.
Increments by 1 when this location is written from the
secondary interface with any data value if bit [31] of this register
is written with a 0 during the same write.
When bit [31] is written with a 1, the 21555 loads the counter
with the value written.
Decrements when the Outbound Queue at offset 44h is read
from the primary interface, except when the counter is zero. The
21555 does not decrement when the counter is 0.
Reset value is 0
30:16 Reserved R Reserved. Read only as 0.
31 LD_OPC W1TL(S)
Load Outbound Post_List Counter.
When written with a 1 at the same time as the Outbound Post
Ctr bits [15:0], it loads the Outbound Post_List Counter with the
value on s_ad[15:0] during that same write.
When written with a 0, or if s_cbe_l[3] is 1, it increments the
Outbound Post_List Counter. Reads always return 0.
Table 94. I2O Outbound Free_List Counter
Byte Offsets: 067:064h
Bit Name R/W Description
15:0 Outbound Free Ctr R/(WS)
When read, returns the number of entries in the Outbound
Free_List.
Decrements by 1 when this location is written from the
secondary interface with any data value when bit [31] of this
register is written with a 0 during the same write.
When bit [31] is written with a 1, the 21555 loads the counter
with the value written.
Increments when the Outbound Queue at offset 44h is written
from the primary interface.
Reset value is 0
30:16 Reserved R Reserved. Read only as 0.
31 LD_OPC W1TL(S)
Load Outbound Free_List Counter.
• When written with a 1 at the same time as the Outbound
Free Ctr bits [15:0], it loads the Outbound Free_List
Counter with the value on s_ad[15:0] during that same
write.
• When written with a 0, or if s_cbe_l[3] is 1, it decrements
the Outbound Free_List Counter. Reads always return 0.