Intel 21555 - Manual (Page 99)

21555 Non-Transparent PCI-to-PCI Bridge User Manual 99
Arbitration
.
Each bus master, including the 21555, may be configured to be in either the low priority group or the high priority
group by setting the corresponding priority bit in the Arbiter Control register in device-specific configuration space.
When the bit is set to a one, the master is assigned to the high priority group. When the bit is set to a zero, the
master is assigned to the low priority group. When all the masters are assigned to one group, the algorithm defaults
to a straight rotating priority among all the masters. After reset, all external masters are assigned to the low priority
group and the 21555 is assigned to the high priority group. The 21555 receives highest priority on the target bus
every other transaction, and priority rotates evenly among the other masters.
Priorities are reevaluated every time s_frame_l is asserted, at the start of each new transaction on the secondary
PCI bus. From this point until the time that the next transaction starts, the arbiter asserts the grant signal
corresponding to the highest priority request that is asserted. When a grant for a particular request is asserted and a
higher priority request subsequently asserts, the arbiter deasserts the asserted grant signal and asserts the grant
corresponding to the new higher priority request on the next PCI clock cycle. The 21555 allocates a two-cycle
minimum assertion time during bus idle once a grant is asserted to a bus master. When priorities are reevaluated,
the highest priority is assigned to the next highest priority master relative to the master that initiated the previous
transaction. The master that initiated the last transaction has the lowest priority in its group.
When the 21555 detects that a master has failed to assert s_frame_l after 16 cycles of both grant assertion and a
secondary idle bus condition, the arbiter deasserts the grant. That master does not receive any more grants until it
deasserts its request for at least one PCI clock cycle.
To prevent bus contention, when secondary FRAME# is deasserted, the arbiter does not assert one grant signal in
the same PCI cycle as it deasserts another. It deasserts one grant, and then asserts the next grant no earlier than one
PCI clock cycle later. When s_frame_l is asserted, the arbiter can deassert one grant and assert another grant during
the same PCI clock cycle.
Figure 25. Secondary Arbiter Example
A7492-01
B
m0
m1
m2
lpg
m6
m7
m8
m4
m5
m3
B = 21555
mx = master # x
lpg = low priority group
Arbiter Control Register = 1000000111b