I2o support 14, 1 inbound message passing, I2o support – Intel 21555 User Manual
Page 113: Inbound message passing, Chapter 14, “i2o support
21555 Non-Transparent PCI-to-PCI Bridge User Manual
113
I2O Support
14
This chapter presents the theory of operation information about the 21555 I20 support. See
for specific
information about I20 registers.
The 21555 implements an I2O messaging unit to allow passing of I2O messages between the host system and the
local subsystem which is called IOP in I2O nomenclature.
For the host system to identify the local subsystem as an I2O compliant IOP, the class code must be preloaded to
indicate I2O support:
•
The Base Class is loaded with the code for intelligent I/O controllers (0Eh).
•
The Sub-class Code is loaded with the code indicating I2O conformance (00h).
•
The Programming Interface is loaded with (01h) to indicate 32-bit data width, 32-bit addressing, little endian,
with support of the outbound post status and mask registers.
•
The I2O Enable bit in the Chip Control 1 configuration register must be set to a 1 to enable the I2O message
unit.
Otherwise, accesses to the I2O Inbound Queue and I2O Outbound Queue result in TRDY# and a discard of data for
memory writes and TRDY#, and return of FFFFFFFFh for memory reads.
The 21555 implements two predefined I2O registers in CSR space that allow access to the I2O Inbound Queue, at
offset 40h, and the I2O Outbound Queue, at offset 44h. The actual queues are located in local memory. Each queue
has a Post_List FIFO and a Free_List FIFO.
•
The Post_List contains I2O Message Frame Addresses (MFAs).
•
The Free_List contains empty MFAs.
The 21555 implements hardware to control the FIFOs from the host side. Control of the FIFOs from the local
processor side is done in software.
14.1
Inbound Message Passing
An inbound message is passed from the host processor to the local processor in the following steps:
1. The host processor removes an empty MFA, if available, from the head of the Inbound Free_List.
2. The host processor posts an MFA containing the address of the message frame to the tail of the Inbound
Post_List.
3. The I2O controller interrupts the local processor, indicating that an MFA exists in the Inbound Post_List.
4. The local processor retrieves the MFA from the head of the Inbound Post_List.
5. After the local processor consumes the message, it replaces the empty MFA onto the tail of the Inbound
Free_List.