Intel 21555 - Manual (Page 43)

21555 Non-Transparent PCI-to-PCI Bridge User Manual 43
Address Decoding
transaction. One pair is used for downstream I/O transactions and one pair is used for upstream I/O transactions.
The downstream registers can only be accessed from the primary interface, and the upstream registers can only be
accessed from the secondary interface. Their function is similar, so only the downstream case is discussed.
The Downstream I/O Address register contains the address used when the transaction is initiated on the secondary
bus. When the Downstream I/O Data register is read or written from the primary interface, the 21555 initiates the
transaction on the secondary bus. For writes, the Downstream I/O Data register contains the write data to be
written. For reads, the read data is placed in this register upon completion of the secondary bus I/O read.
The I/O Data register must be accessed with an I/O transaction on the primary interface to initiate the secondary bus
I/O transaction. Otherwise, this register appears as reserved for both memory accesses or accesses from the
secondary interface. The Downstream I/O Control bit in the I/O CSR must be set to enable downstream I/O
transaction generation; otherwise, I/O Data register accesses are treated as reserved accesses.
The 21555 uses the same byte enables that the initiator used to read or write the register.
Note: The low bits of the I/O address in the I/O Address register must match the byte enables as
described in the PCI Local Bus Specification, Revision 2.2. The 21555 will not correct
discrepancies between byte enables and address bits [1:0].
The 21555 responds to read or write access of Downstream I/O Data register with a target retry until the access is
completed on the secondary bus. This I/O access is treated as a delayed transaction by the 21555. This delayed
transaction is entered into the 21555’s downstream delayed transaction queue and is ordered with respect to all
other downstream transactions. When ordering rules permit, the 21555 initiates I/O write or read on the secondary
bus. When the I/O transaction completes, the 21555 returns target termination and, if a read, returns read data when
the initiator repeats the transaction.
The 21555 provides a semaphore method that may be used to guarantee atomicity of the Downstream I/O Address
and Downstream I/O Data register accesses using the Downstream I/O Own bit. Atomicity of these accesses is not
hardware-enforced. An Upstream I/O Own bit is provided for upstream I/O transactions. The following procedure
should be used for downstream
I/O transactions:
1. The initiator of the transaction reads the Downstream I/O Own bit. When the bit reads as zero, the initiator can
proceed with the indirect I/O transaction sequence. When the bit reads as a 1, the initiator should not proceed
until a subsequent read of the own bit returns a 0 (zero). The 21555 automatically sets the own bit to a 1after it
is read from the primary interface.
2. The initiator writes the target I/O address in the Downstream I/O Address register.
3. The initiator should write or read the data in the Downstream I/O Data register until a response other than
target retry is received.
4. Upon returning the completion of the I/O transaction to the initiator, the 21555 automatically clears the bit to a
0.
The same procedure should be used for upstream I/O transactions using the Upstream I/O Address register,
Upstream I/O Data register, and Upstream I/O Own bit. To read the state of the Downstream and Upstream I/O
Own bits without side effects, a read-only copy of the I/O Own bit states is kept in the I/O CSR. Byte access of the
I/O Own bits and their
read-only copies should be used to avoid setting the I/O Own bit for the opposite interface.