Intel 21555 - Manual (Page 191)

21555 Non-Transparent PCI-to-PCI Bridge User Manual 191
List of Registers
Table 129. Boundary Scan Order
TBD table lists the boundary-scan register order and the group disable controls. The group disable control either
enables or tristates its corresponding group of bi-directional drivers. When the value of a group disable control bit is
0, the output driver is enabled. When the value is 1, the driver is
tri-stated. There are TBD groups of bi-directional drivers, and therefore TBD group disable control bits.
0011 CLAMP Bypass
Drives pins from the boundary - scan
register and selects the bypass
register for shifts.
0100
IDCODE
†
Idcode
Reads the manufacturer’s
identification number, the design part
number, and the design version
number.
0101 - 1111 BYPASS Bypass Selects the bypass register for shifts.
Table 127. Bypass Register
The bypass register is a 1-bit shift register that provides a means for effectively bypassing the
JTAG test logic through a single-bit serial connection through the device from tdi to tdo.
At board-level testing, this helps reduce the overall length of the scan ring.
Table 128. Boundary - Scan Register
The boundary - scan register (BSR) is a single - shift register - based path formed by boundary - scan cells placed
at the device’s signal pins. The register is accessed through the tdi and tdo pins of the JTAG port.
Each boundary - scan cell operates in conjunction with the current instruction and the current state in the test
access port controller state machine. The function of the BSR cells is determined by the Input, Output, and
Bidirectional pins.
Pin Description
Input - only pins
The boundary - scan cell is basically a 1 - bit shift register. The cell supports sample and
shift operations.
Output - only pins
The boundary - scan cell comprises a 1 - bit shift register and an output multiplexer. The cell
supports the sample, shift, and drive output functions.
Bidirectional
pins:
The boundary - scan cell is identical to the output - only pin cell, but it captures test data
from the incoming data line. The cell supports sample, shift, drive output, and hold output
functions.
Table 126. JTAG Instruction Register Options (Sheet 2 of 2)
The 4-bit instruction register selects the test mode and features. The instruction codes are shown
in
Table 126 . These instructions select and control the operation of the boundary-scan and bypass
registers. The instruction register is loaded through the tdi pin. The instruction register has a
serial shift-in stage from which the instruction is then loaded in parallel.
Instruction Register
Contents Instruction
Name Test Register
Selected
Operation
† Manufacturer’s identification number: 0000 0001 0011
Design part number: 1001 0010 0110 0010
Version: 0000