Intel 21555 - Manual (Page 117)

21555 Non-Transparent PCI-to-PCI Bridge User Manual 117
I2O Support
• All MFA counters maintained by the 21555 may be individually loaded with any data value by writing a 1 to
bit 31 of the corresponding counter Dword offset. When either the Inbound Free_List Counter or the Outbound
Post_List Counter is loaded, the 21555 discards any prefetched data in the corresponding prefetch buffer.
• The 21555 actions are unpredictable in response to primary bus transactions addressing the I2O Outbound or
Inbound Queues while a corresponding counter load is occurring on the secondary bus. The counters will load
and increment even if the I2O Enable is not set.
• The 21555 I2O counters are consistent with the number of entries in the various lists from the secondary bus,
or local memory, point of view. This means that counters do not include any MFAs that exist in the 21555
posting or prefetch buffers. The counters include only those entries that are present in local memory. The
Outbound Free_List and Inbound Post_List pointers are consistent with the primary bus viewpoint. This means
that the value of the head and tail pointers that the 21555 implements includes any data in the 21555 posted
write buffers as part of the lists. The pointers corresponding to the Outbound Post_List and Inbound Free_List
should not be considered to be consistent with the number of entries in these lists.
• The 21555 I2O counters are consistent with the number of entries in the various lists from the secondary bus,
or local memory, point of view. This means that counters do not include any MFAs that exist in the 21555
posting or prefetch buffers. The counters include only those entries that are present in local memory.
• When the I2O Enable bit is disabled after the I2O message unit is operational, additional reads to 40h and 44h
returns data that remains in the corresponding prefetch buffer until the prefetch buffer is emptied. After the
prefetch buffer is emptied, the 21555 returns FFFF FFFFh.
• When the secondary interface Master Enable bit is disabled:
— Reads to 40h and 44h are FFFF FFFFh.
— Writes to 40h and 44h are queued in the downstream posted write queue, but not delivered until the master
enable bit is set.