Intel 21555 - Manual (Page 144)

144 21555 Non-Transparent PCI-to-PCI Bridge User Manual
List of Registers
9
Upstream
Configuration
Control
R/W
Enables the 21555 to perform upstream indirect configuration
transactions.
• When 0, the 21555 will not initiate a configuration transaction on the
primary interface when the Upstream Configuration Data register is
accessed. The Upstream Configuration Data register is treated as a
reserved register.
• When 1, the 21555 is enabled to perform upstream configuration
transactions when the Upstream Configuration Data register is
accessed.
• Reset value is 0
10
Upstream
Self
- Response
Enable
R/W
Controls the 21555 ability to respond to a configuration transaction that it
generates as a master.
• When 0, the 21555 does not respond to configuration transactions
that it generates. These transaction end in master abort.
• When 1, the 21555 does not respond to configuration transactions
that it generates as a master.
• Reset value is 0
15:11 Reserved R Reserved. Reads only as 0.
Table 50. Downstream I/O Address and Upstream I/O Address Registers
The Downstream I/O Address register is used for I/O transactions to be initiated on the secondary bus, and
the Upstream I/O Address register is used for I/O transactions to be initiated on the primary bus. The
downstream register can be written from the primary interface only and the upstream register can be written
from the secondary interface only
.
Bit Name R/W Description
31:0 IO_ADDR (IA)
DIA:
R/(WP)
UIA:
R/(WS)
This register contains the address for an I/O transaction to be
generated on the target bus. The address is driven exactly as written
in this register. This register should be written before the Downstream
or Upstream I/O Data register is accessed. Once the Downstream or
Upstream I/O Data register is written or read, the transaction is
initiated on the secondary bus. When the semaphore method is used,
a master should not write to this register unless the master has
successfully read a 0 from the Downstream or Upstream I/O Own bit.
Reset value is 0
Table 49. Configuration CSR (Sheet 2 of 2)
This register is also mapped in memory and I/O space.
• Primary byte offset: 93:92h
• Secondary byte offset: 93:92h
• CSR byte offset: 013:012h
Bit Name R/W Description
Offset Downstream I/O Address Upstream I/O Address
Byte 017:014h 1F:1Ch