Intel 21555 - Manual (Page 163)

21555 Non-Transparent PCI-to-PCI Bridge User Manual 163
List of Registers
3
Downstream
Posted Write
Data
Discarded
R/W1TC
This bit is set to a 1 and p_serr_l is conditionally asserted when the
21555 discards a downstream posted write transaction after receiving
2
24 target retries from the secondary bus target (Retry counters must
not be disabled).
Reset value is 0
7:4 Reserved R Reserved. Returns 0 when read.
8
Upstream
Delayed
Transaction
Master
Time
- out
R/W1TC
This bit is set to a 1 and s_serr_l is conditionally asserted when the
secondary master timeout counter expires and an upstream delayed
transaction completion is discarded from the 21555’s queues.
Reset value is 0
9
Upstream
Delayed
Read
Transaction
Discarded
R/W1TC
This bit is set to a 1 and s_serr_l is conditionally asserted when the
21555 discards an upstream delayed read transaction request after
receiving 2
24 target retries from the primary bus target (Retry
counters must not be disabled).
Reset value is 0
10
Upstream
Delayed
Write
Transaction
Discarded
R/W1TC
This bit is set to a 1 and s_serr_l is conditionally asserted when the
21555 discards an upstream delayed write transaction request after
receiving 2
24 target retries from the primary bus target (Retry
counters must not be disabled).
Reset value is 0
11
Upstream
Posted Write
Data
Discarded
R/W1TC
This bit is set to a 1 and s_serr_l is conditionally asserted when the
21555 discards an upstream posted write transaction after receiving
2
24 target retries from the primary bus target (Retry counters must not
be disabled).
Reset value is 0
15:12 Reserved R Reserved. Returns 0 when read.
Table 79. Chip Status Register
All of the following conditions can cause the assertion of p_serr_l or s_serr_l if the corresponding SERR#
enable bit is set and the disable bit for this condition is not set.
• Primary byte offset: D1:D0h
• Secondary byte offset: D1:D0h
Bit Name R/W Description