Intel 21555 - Manual (Page 60)

60 21555 Non-Transparent PCI-to-PCI Bridge User Manual
PCI Bus Transactions
5.6 Target Terminations
This section describes the following target retries, target disconnects, and target aborts received and returned by the
21555.
• Section 5.6.1, “Target Terminations Returned by the 21555” on page 60 .
• Section 5.6.2, “Transaction Termination Errors on the Target Bus” on page 61 .
• Section 5.6.2, “Transaction Termination Errors on the Target Bus” on page 61 .
5.6.1 Target Terminations Returned by the 21555
The 21555 returns a target retry under the following circumstances:
• Queue is full for posted memory writes.
• Delayed transaction is queued but response is not ready.
• Queue is full for delayed transactions. The delayed transaction is not queued.
• Serial preload is ongoing.
• Primary Lockout Bit is set for primary bus transactions.
• Transaction is in progress for CSR generation of I/O or Configuration Access (delayed transaction not ready).
• The 21555 is discarding read data.
Target disconnects by the 21555 always consist of STOP# asserted and TRDY# deasserted (that is, a target
disconnect without data transfer). The 21555 returns a target disconnect under the following circumstances:
• Queue fills during posted write.
• Cache line boundary is reached for MWI transaction and the 21555 cannot buffer another cache line.
• Cache line boundary is reached for memory write transaction and the Memory Write
Disconnect bit is set.
• The 21555 runs out of read data during completion of delayed transaction to the initiator.
• The 21555 is responding to a nonprefetchable Read transaction if multiple data phases are requested by the
initiator.
• Multiple data phases requested by the initiator for an I/O or configuration access.
• Low two address bits of the transaction are non-zero.
The 21555 returns a target abort and sets the Signaled Target Abort bit in the Primary and Secondary Status register
under the following circumstances:
• Target abort is detected during a delayed transaction completion on the target bus.
• Master abort is detected in response to a delayed transaction on the target bus when the Master Abort Mode bit
is set to a 1. See
Table 77, “Chip Control 0 Register” on page 156 .
• Delayed transaction request is discarded after 2
24
target retries received from the target.
• Invalid lookup table entry is encountered when forwarding upstream transactions in Upstream Memory 2 range
and the Master Abort Mode bit is set to a 1.