Chip control 1 register – Intel 21555 User Manual
Page 160
160
21555 Non-Transparent PCI-to-PCI Bridge User Manual
List of Registers
Table 78. Chip Control 1 Register (Sheet 1 of 3)
This register may be preloaded by serial ROM or programmed by the local processor before host
configuration.
•
Primary byte offset: CF:CEh
•
Secondary byte offset: CF:CEh
Bit
Name
R/W
Description
0
Primary
Posted Write
Threshold
R/W
Controls the queue full threshold limit of the downstream posted write
queue. When the queue is designated full, the 21555 returns retry to posted
writes on the primary bus. Otherwise, the 21555 accepts write data into the
posted write queue.
•
When 0, posted write queue full when less than a cache line is free to
post data.
•
When 1, posted write queue full when less than a half cache line (for
CLS=8,16,32) is free to post data.
•
Reset value is 0b
1
Secondary
Posted Write
Threshold
R/W
Controls the queue full threshold limit of the upstream posted write queue.
When the queue is designated full, the 21555 returns retry to posted writes
on the secondary bus. Otherwise, the 21555 accepts write data into the
posted write queue.
•
When 0, posted write queue full when less than a cache line is free to
post data.
•
When 1, posted write queue full when less than a half cache line (for
CLS=8,16,32) is free to post data.
•
Reset value is 0b
3:2
Primary
Delayed
Read
Threshold
R/W
Controls the read data queue threshold for initiating read transactions on
the primary bus. When the amount of read data in the queue exceeds the
threshold, the 21555 does not initiate a pending upstream delayed memory
read transaction on the primary bus. The following values control when the
21555 initiates a memory read:
•
00b: At least 8 Dwords free in read data queue for all memory read
commands
•
01b: Illegal (uses the same behavior as 00b)
•
10b: At least one cache line free for MRL and MRM, 8 Dwords free for
memory read
•
11b: At least one cache line free for all memory read commands
NOTE: The secondary bus cache line size is used for the threshold
calculation.
Reset value is 00b
5:4
Secondary
Delayed
Read
Threshold
R/W
Controls the read data queue threshold for initiating read transactions on
the secondary bus. When the amount of read data in the queue exceeds
the threshold, the 21555 does not initiate a pending downstream delayed
memory read transaction on the secondary bus. The following values
control when the 21555 initiates a memory read:
•
00b: At least 8 Dwords free in read data queue for all memory read
commands
•
01b: Illegal (uses the same behavior as 00b)
•
10b: At least one cache line free for MRL and MRM, 8 Dwords free for
memory read
•
11b: At least one cache line free for all memory read commands
NOTE: The primary bus cache line size is used for the threshold
calculation.
Reset value is 00b