Intel 21555 - Manual (Page 82)

82 21555 Non-Transparent PCI-to-PCI Bridge User Manual
Parallel ROM Interface
Table 21. PROM Interface Signals (Sheet 1 of 2)
Signal
Name
Type Description
pr_ad[7:0] TS
These signals interface to both the serial and parallel external ROM circuitry and
have multiple functions.
The signals pr_ad[7:0] serve as multiplexed address/data for the PROM and are
latched externally in the following sequence:
• Address [23:16] during the first address cycle.
• Address [15:8] during the second address cycle.
• Address [7:0] during the third address cycle.
• Data [7:0] during the data cycle.
The signals pr_ad[2:0] also serve as serial ROM signals, with no external logic
required:
• pr_ad[2]: sr_do, the serial ROM data output.
• pr_ad[1]: sr_di, the serial ROM data input.
• pr_ad[0]: sr_ck, the serial ROM clock output.
The value of pr_ad[7:1] signals during chip reset specifies the configuration options
in the bit descriptions that follow. The values of these configuration options may be
read from the
Table 113, “Mode Setting Configuration Register” on page 179 .
pr_ad[7]
Arbiter enable (active high). When low, the secondary bus arbiter is disabled,
s_gnt_l[0] is used for 21555 secondary bus request, and s_req_l[0] is used for
21555 secondary bus grant. When high, the internal arbiter is enabled for use.
pr_ad[6]
Central function enable (active low). When low, the 21555 drives s_ad, s_cbe_l, and
s_par low during secondary reset. When the secondary PCI interface is 64 bits, the
21555 also drives s_req64_l low. When high, the 21555 tristates s_req64_l, s_ad,
s_cbe_l, and s_par during secondary reset.
pr_ad[5]
Signal s_clk_o enable (active high). When low, s_clk_o is turned off and driven low.
When high, s_clk_o is turned on and is a buffered version of p_clk.
pr_ad[4]
Synchronous enable (active low). When high, the 21555 assumes asynchronous
primary and secondary interfaces. When low, the 21555 assumes synchronous
primary and secondary interfaces.
pr_ad[3]
Primary lockout bit reset value. When high, the primary lockout bit is set high upon
completion of chip reset, causing the 2155X to return target retry to primary bus
transactions until the bit is cleared. When low, the primary lockout bit is cleared low
upon completion of reset, allowing immediate access to configuration registers.
pr_ad[2]
When the serial ROM is not connected, this pin should be pulled either high or low to
disable the register preload. When the preload sequence 10b is not detected during
the first read, the serial ROM preload is terminated after the first two bits are read and
the 21555 registers remain at their reset values. This is not actually sampled at reset,
but during the first serial ROM read.
pr_ad[1]
When the s_rst_in_l signal is used to reset the chip, sampling this signal low upon
deassertion of s_rst_in_l enables the primary bus 64-bit extension. Sampling this
signal high upon deassertion of s_rst_in_l disables the primary bus 64-bit extension,
and those signals are then driven to valid logic values.