Intel 21555 - Manual (Page 146)

146 21555 Non-Transparent PCI-to-PCI Bridge User Manual
List of Registers
Table 53. I/O CSR
• Byte Offset: 027:026h
Bit Name R/W Description
0
Downstream
I/O Own Bit
Status
R
This bit reflects the status of the Secondary Own bit used for
generating I/O transaction on the secondary bus.
• When 0, the Downstream I/O Address and Downstream I/O
Data registers are not owned.
• When 1, the Downstream I/O Address and Downstream I/O
Data registers are owned by a master.
1
Downstream
I/O Control
R/W
Enables the 21555 to perform downstream indirect I/O transactions.
• When 0, the 21555 will not initiate a I/O transaction on the
secondary interface when the Downstream I/O Data register is
accessed. The Downstream I/O Data register is treated as a
reserved register.
• When 1, the 21555 is enabled to perform downstream I/O
transactions when the Downstream I/O Data register is
accessed with an I/O transaction.
• Reset value is 0
7:2 Reserved R Reserved. Read only as 0.
8
Upstream
I/O Own Bit
Status R
This bit reflects the status of the Primary Own bit used for generating
I/O transaction on the Primary bus.
• When 0, the Upstream I/O Address and Upstream I/O Data
registers are not owned.
• When 1, the Upstream I/O Address and Upstream I/O Data
registers are owned by a master.
9
Upstream
I/O Control
R/W
Enables the 21555 to perform upstream indirect I/O transactions.
• When 0, the 21555 will not initiate an I/O transaction on the
primary interface when the Upstream I/O Data register is
accessed. The Upstream I/O Data register is treated as a
reserved register.
• When 1, the 21555 is enabled to perform upstream I/O
transactions when the Upstream I/O Data register is accessed
with an
I/O transaction.
• Reset value is 0
15:10 Reserved R Reserved. Read only as 0.
Table 54. Lookup Table Offset Register
Table 54 and Table 55 are registers that provide a method for the lookup table to be accessed using I/O
transactions, although memory transactions can use either this mechanism or direct access of the lookup
table.
• Byte Offset: 028h
Bit Name R/W Description
7:0 LUT_OFFSET R/W
This register contains the byte offset of the Lookup Table entry to be
accessed. The access is initiated when the Lookup Table Data register
is either read or written. This register should be written before the
Lookup Table Data register is accessed.