Intel 21555 - Manual (Page 79)

21555 Non-Transparent PCI-to-PCI Bridge User Manual 79
Clocking
7.3 66 MHz Support
The 21555 supports 66 MHz operation. It has two pins, p_m66ena and s_m66ena, that indicate whether the
primary and secondary bus are operating at 66 MHz, respectively. Signal p_m66ena is an input-only pin.
• When sampled high, the primary bus is assumed to be operating at 66 MHz.
• When sampled low, the primary bus must be operating at or below 33 MHz. Signal s_m66ena is an input/
open-drain pin.
• When sampled high, the secondary bus is assumed to be operating at 66 MHz.
• When sampled low, the secondary bus must be operating at or below 33 MHz.
The 21555 pulls s_m66ena low when the primary bus is operating at 33 MHz (p_m66ena low) and s_clk_o is
enabled. When s_clk_o is enabled, it is assumed that the 21555 is controlling the clocking of the secondary bus and
since s_clk_o is a buffered version of p_clk, it must operate at
33 MHz.
When p_m66ena is sampled high, s_m66ena is sampled low, and s_clk_o is enabled, the 21555 divides s_clk_o by
2 to generate a 33Mhz clock.
The 21555 can handle any combination of clock frequencies between primary and secondary buses with the
maximum clock ratio between primary and secondary buses being 2.5:1 (for example 25 MHz on one bus and 66
MHz on the other), and a maximum frequency of 66 MHz.