Srom write all timing diagram, Srom write enable timing diagram, Srom write disable timing diagram – Intel 21555 User Manual
Page 94: Figure 19
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21555 Non-Transparent PCI-to-PCI Bridge User Manual
Serial ROM Interface
Note:
When a SROM access using the CSR mechanism is attempted when the SROM is not
implemented, the ROM interface may hang. This prevents access to any PROMs that may be
present. A chip reset may be needed to put the ROM interface in an operational state
.
Figure 19. SROM Write All Timing Diagram
Figure 20. SROM Write Enable Timing Diagram
Figure 21. SROM Write Disable Timing Diagram
A7476-01
pr_ad[1]
(sr_di)
pr_ad[2]
(sr_do)
sr_cs
pr_ad[0]
(sr_ck)
1
1
0
0
0
X
X
D0
D1
D7
A7477-01
X
X
pr_ad[1]
(sr_di)
sr_cs
pr_ad[0]
(sr_ck)
1
1
0
0
1
A7478-01
X
X
pr_ad[1]
(sr_di)
sr_cs
pr_ad[0]
(sr_ck)
1
0
0
0
0
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