Intel 21555 User Manual
Page 123
21555 Non-Transparent PCI-to-PCI Bridge User Manual
123
List of Registers
2F:2E
6F:6E
Subsystem ID Register, page
154
0000
Y
Secondary
Y
33:30 (P)
73:70 (S)
Primary Expansion ROM BAR,
page 175
00000000
Via Setup
Via Setup
Y
34
74
Enhanced Capabilities Pointer
Register, page 154
DC
—
N
Y
37:35 (P)
77:75 (S)
Reserved
000000
—
N
Y
3B:38 (P)
7B:78 (S)
Reserved
00000000
—
N
Y
3C (P)
7C (S)
Primary and Secondary Interrupt
Line Registers, page 154
00
—
Y
Y
3D (P)
7D (S)
Primary and Secondary Interrupt
Pin Registers, page 155
01
—
N
Y
3E (P)
7E (S)
Primary and Secondary Minimum
Grant Registers, page 155
00
Y
Secondary
Y
3F (P)
7F (S)
Primary and Secondary
Maximum Latency Registers,
page 155
00
Y
Secondary
Y
45:44 (P)
05:04 (S)
Primary and Secondary
Command Registers, page 149
0000
47:46 (P)
07:06 (S)
Primary and Secondary Status
Registers, page 150
0290
—
Y
Y
4B:49 (P)
0B:09 (S)
Primary and Secondary Class
Code Registers, page 152
068000
Y
N
Y
4C (P)
0C (S)
Primary and Secondary Cache
Line Size Registers, page 152
00
—
Y
Y
4D (P)
0D (S)
Primary Latency and Secondary
Master Latency Timer Registers,
page 153
00
—
Y
Y
53:50 (p)
13:10 (s)
Secondary CSR Memory BAR
00000000
—
Y
Y
57:54 (p)
17:14 (s)
Secondary CSR I/O BAR
00000001
—
Y
Y
5B:58 (P)
1B:18 (S)
Upstream I/O or Memory 0 BAR
00000000
Via Setup
Via Setup
Y
5F:5C (P)
1F:1C (S)
Upstream Memory 1 BAR
00000000
Via Setup
Via Setup
Y
63:60 (P)
23:20 (S)
Upstream Memory 2 BAR
00000000
Via Chip
Control 1
Via Chip
Control 1
Y
67:64 (P)
27:24 (S)
Reserved
00000000
—
N
Y
73:70 (P)
33:30 (S)
Reserved
00000000
—
N
Y
7C(P)
3C (S)
Primary and Secondary Interrupt
Line Registers, page 154
00
—
Y
Y
Table 32. Configuration Space Address Register (Sheet 2 of 5)
Byte
Offset
(Hex)
Register Name
Reset Value
(Hex)
Preload
Write
Access
Read
Access