Samsung S3C2440A - Manual (Page 147)

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR
4-26
FORMAT 11: SP-RELATIVE LOAD/STORE
[7:0] Immediate Value
[10:8] Destination Register
[11] Load/Store Bit
0 = Store to memory
1 = Load from memory
15 0
1
14 10
0 0
13 12 11
Word 8 1 L Rd
7 8
Figure 4-12. Format 11
OPERATION
The instructions in this group perform an SP-relative load or store. The THUMB assembler syntax is shown in the
following table.
Table 4-12. SP-Relative Load/Store Instructions
L THUMB assembler ARM equivalent Description
0 STR Rd, [SP, #Imm] STR Rd, [R13 #Imm] Add unsigned offset (255 words, 1020
bytes) in Imm to the current value of the SP
(R7). Store the contents of Rd at the
resulting address.
1 LDR Rd, [SP, #Imm] LDR Rd, [R13 #Imm] Add unsigned offset (255 words, 1020
bytes) in Imm to the current value of the SP
(R7). Load the word from the resulting
address into Rd.
NOTE
The offset supplied in #Imm is a full 10-bit address, but must always be word-aligned (ie bits 1:0 set to 0),
since the assembler places #Imm >> 2 in the Word8 field.