Samsung S3C2440A - Manual (Page 315)

S3C2440A RISC MICROPROCESSOR UART
11-11
UART CONTROL REGISTER
There are three UART control registers including UCON0, UCON1 and UCON2 in the UART block.
Register Address R/W Description Reset Value
UCON0 0x50000004 R/W UART channel 0 control register 0x00
UCON1 0x50004004 R/W UART channel 1 control register 0x00
UCON2 0x50008004 R/W UART channel 2 control register 0x00
UCONn Bit Description Initial State
FCLK divider [15:12] Divider value when the Uart clock source is selected as FCLK/n.
’n’ is determined by UCON0[15:12], UCON1[15:12], UCON2[14:12].
UCON2[15] is FCLK/n Clock Enable/Disable bit.
For setting ‘n’ from 7 to 21, use UCON0[15:12],
For setting ‘n’ from 22 to 36, use UCON1[15:12],
For setting ‘n’ from 37 to 43, use UCON2[14:12],
UCON2[15]: 0 = Disable FCLK/n clock. 1 = Enable FCLK/n clock.
In case of UCON0,
UART clock = FCLK / (divider+6), where divider>0.
UCON1, UCON2 must be zero.
ex) 1: UART clock = FCLK/7, 2: UART clock = FCLK/8
3: UART clock = FCLK/9, … , 15: UART clock = FCLK/21
In case of UCON1,
UART clock = FCLK / (divider+21), where divider>0.
UCON0, UCON2 must be zero.
ex) 1: UART clock = FCLK/22, 2: UART clock = FCLK/23
3: UART clock = FCLK/24, … , 15: UART clock = FCLK/36
In case of UCON2,
UART clock = FCLK / (divider+36), where divider>0.
UCON0, UCON1 must be zero.
ex) 1: UART clock = FCLK/37, 2: UART clock = FCLK/38
3: UART clock = FCLK/39, … , 7: UART clock = FCLK/43
If UCON00/1[15:12] and UCON2[14:12] are all ‘0’, the divider will be
44, that is UART clock = FCLK/44
Total division range is from 7 to 44.
0000
Clock Selection [11:10] Select PCLK, UEXTCLK or FCLK/n for the UART baud rate.
UBRDIVn = (int)(selected clock / (baudrate x 16) ) –1
00, 10 = PCLK 01 = UEXTCLK 11 = FCLK/n
(If you would select FCLK/n, you should add the code of “NOTE”
after selecting or deselecting the FCLK/n.)
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