Samsung S3C2440A - Manual (Page 361)

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER
14-11
INTERRUPT MASK (INTMSK) REGISTER
This register also has 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the CPU
does not service the interrupt request from the corresponding interrupt source (note that even in such a case, the
corresponding bit of SRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced.
Register Address R/W Description Reset Value
INTMSK 0X4A000008 R/W Determine which interrupt source is masked. The masked
interrupt source will not be serviced.
0 = Interrupt service is available.
1 = Interrupt service is masked.
0xFFFFFFFF