Samsung S3C2440A - Manual (Page 324)

UART S3C2440A RISC MICROPROCESSOR
11-20
UART TRANSMIT BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER)
There are three UART transmit buffer registers including UTXH0, UTXH1 and UTXH2 in the UART block.
UTXHn has an 8-bit data for transmission data.
Register Address R/W Description Reset Value
UTXH0 0x50000020(L)
0x50000023(B)
W
(by byte)
UART channel 0 transmit buffer register -
UTXH1 0x50004020(L)
0x50004023(B)
W
(by byte)
UART channel 1 transmit buffer register -
UTXH2 0x50008020(L)
0x50008023(B)
W
(by byte)
UART channel 2 transmit buffer register -
UTXHn Bit Description Initial State
TXDATAn [7:0] Transmit data for UARTn -
Note
(L): The endian mode is Little endian.
(B): The endian mode is Big endian.
UART RECEIVE BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER)
There are three UART receive buffer registers including URXH0, URXH1 and URXH2 in the UART block.
URXHn has an 8-bit data for received data.
Register Address R/W Description Reset Value
URXH0 0x50000024(L)
0x50000027(B)
R
(by byte)
UART channel 0 receive buffer register -
URXH1 0x50004024(L)
0x50004027(B)
R
(by byte)
UART channel 1 receive buffer register -
URXH2 0x50008024(L)
0x50008027(B)
R
(by byte)
UART channel 2 receive buffer register -
URXHn Bit Description Initial State
RXDATAn [7:0] Receive data for UARTn -
Note
When an overrun error occurs, the URXHn must be read. If not, the next received data will also make an overrun error, even
though the overrun bit of UERSTATn had been cleared.