Samsung S3C2440A User Manual
Page 458
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IIC-BUS INTERFACE
S3C2440A RISC MICROPROCESSOR
20-10
IIC detects start signal. and, IICDS
receives data.
IIC compares IICADD and IICDS (the
received slave address).
Read data from IICDS.
The IIC address match
interrupt is generated.
Clear pending bit to
resume.
SDA is shifted to IICDS.
START
Slave Rx mode has
been configured.
END
Matched?
N
Y
Stop?
Interrupt is pending.
N
Y
Figure 20-9 Operations for Slave/Receiver Mode
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