Samsung S3C2440A - Manual (Page 366)

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR
14-16
INTERRUPT OFFSET (INTOFFSET) REGISTER
The value in the interrupt offset register shows which interrupt request of IRQ mode is in the INTPND register.
This bit can be cleared automatically by clearing SRCPND and INTPND.
Register Address R/W Description Reset Value
INTOFFSET 0X4A000014 R Indicate the IRQ interrupt request source 0x00000000
INT Source The OFFSET value INT Source The OFFSET value
INT_ADC 31 INT_UART2 15
INT_RTC 30 INT_TIMER4 14
INT_SPI1 29 INT_TIMER3 13
INT_UART0 28 INT_TIMER2 12
INT_IIC 27 INT_TIMER1 11
INT_USBH 26 INT_TIMER0 10
INT_USBD 25 INT_WDT_AC97 9
INT_NFCON 24 INT_TICK 8
INT_UART1 23 nBATT_FLT 7
INT_SPI0 22 INT_CAM 6
INT_SDI 21 EINT8_23 5
INT_DMA3 20 EINT4_7 4
INT_DMA2 19 EINT3 3
INT_DMA1 18 EINT2 2
INT_DMA0 17 EINT1 1
INT_LCD 16 EINT0 0
Note
FIQ mode interrupt does not affect the INTOFFSET register as the register is available only for IRQ mode
interrupt.