Samsung S3C2440A - Manual (Page 171)

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR
5-6
nXBREQ/nXBACK Pin Operation
If nXBREQ is asserted, the S3C2440A will respond by lowering nXBACK. If nXBACK=L, the address/data bus and
memory control signals are in Hi-Z state as shown in Table 1-1. After nXBREQ is de-asserted, the nXBACK will
also be de-asserted.
HCLK
SCKE, A[24:0]
D[31:0], nGCS
nOE,nWE
nWBE
nXBREQ
nXBACK
SCLK
1clk
Figure 5-3. S3C2440A nXBREQ/nXBACK Timing Diagram