Samsung S3C2440A - Manual (Page 409)

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER
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Register Setting Guide (STN)
The LCD controller supports multiple screen sizes by special register setting.
The CLKVAL value determines the frequency of VCLK. This value has to be determined such that the VCLK value
is greater than data transmission rate. The data transmission rate for the VD port of the LCD controller is used to
determine the value of CLKVAL register.
The data transmission rate is given by the following equation:
Data transmission rate = HS x VS x FR x MV
HS: Horizontal LCD size
VS: Vertical LCD size
FR: Frame rate
MV: Mode dependent value
Table 15-6. MV Value for Each Display Mode
Mode MV Value
Mono, 4-bit single scan display 1/4
Mono, 8-bit single scan display or 4-bit dual scan display 1/8
4 level gray, 4-bit single scan display 1/4
4 level gray, 8-bit single scan display or 4-bit dual scan display 1/8
16 level gray, 4-bit single scan display 1/4
16 level gray, 8-bit single scan display or 4-bit dual scan display 1/8
Color, 4-bit single scan display 3/4
Color, 8-bit single scan display or 4-bit dual scan display 3/8
The LCDBASEU register value is the first address value of the frame buffer. The lowest 4 bits must be eliminated
for burst 4 word access. The LCDBASEL register value depends on LCD size and LCDBASEU. The LCDBASEL
value is given by the following equation:
LCDBASEL = LCDBASEU + LCDBASEL offset