Samsung S3C2440A - Manual (Page 231)

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR
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CLOCK DIVIDER CONTROL (CLKDIVN) REGISTER
Register Address R/W Description Reset Value
CLKDIVN 0x4C000014 R/W Clock divider control register 0x00000000
CLKDIVN Bit Description Initial State
DIVN_UPLL [3] UCLK select register(UCLK must be 48MHz for USB)
0: UCLK = UPLL clock
1: UCLK = UPLL clock / 2
Set to 0, when UPLL clock is set as 48Mhz
Set to 1. when UPLL clock is set as 96Mhz. 0
HDIVN [2:1] 00 : HCLK = FCLK/1.
01 : HCLK = FCLK/2.
10 : HCLK = FCLK/4 when CAMDIVN[9] = 0.
HCLK= FCLK/8 when CAMDIVN[9] = 1.
11 : HCLK = FCLK/3 when CAMDIVN[8] = 0.
HCLK = FCLK/6 when CAMDIVN[8] = 1.
00
PDIVN [0] 0: PCLK has the clock same as the HCLK/1.
1: PCLK has the clock same as the HCLK/2. 0