Samsung S3C2440A - Manual (Page 400)

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR
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LCD Control 5 Register (Continued)
LCDCON5 Bit Description Initial state
INVVDEN [6] TFT: This bit indicates the VDEN signal polarity.
0 = normal
1 = inverted
0
INVPWREN [5]
STN/TFT: This bit indicates the PWREN signal polarity.
0 = normal
1 = inverted
0
INVLEND [4] TFT: This bit indicates the LEND signal polarity.
0 = normal
1 = inverted
0
PWREN [3] STN/TFT: LCD_PWREN output signal enable/disable.
0 = Disable PWREN signal
1 = Enable PWREN signal
0
ENLEND [2] TFT: LEND output signal enable/disable.
0 = Disable LEND signal
1 = Enable LEND signal
0
BSWP [1] STN/TFT: Byte swap control bit.
0 = Swap Disable
1 = Swap Enable
0
HWSWP [0] STN/TFT: Half-Word swap control bit.
0 = Swap Disable
1 = Swap Enable
0