Samsung S3C2440A - Manual (Page 187)

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR
6-2
BLOCK DIAGRAM
zmy
ljjGnΥU
z›Œ——•ŽGz›–•Œ
O[riGzyhtP
z›Œ——•ŽGz›–•Œ
j–•›™–““Œ™
S
YST
EM BU
S
uhukGmshzo
p•›Œ™ˆŠŒ
CLE
ALE
nFCE
nFRE
nFWE
FRnB
I/O0 - I/O15 hoi
z“ˆŒGpVm
j–•›™–“GM
z›ˆ›ŒGtˆŠ•Œ
Figure 6-1 NAND Flash Controller Block Diagram
BOOT LOADER FUNCTION
z›Œ——•ŽGz›–•Œ
O[riGiœŒ™P
uhukGmshzo
j–•›™–““Œ™
uhukGmshzo
tŒ”–™
z—ŒŠˆ“Gmœ•Š›–•
yŒŽš›Œ™š
REGISTERS AUTO BOOT
CORE ACCESS
(Boot Code)
USER ACCESS
Figure 6-2 NAND Flash Controller Boot Loader Block Diagram
During reset, Nand flash controller will get information about the connected NAND flash through Pin status
(NCON(Adv flash), GPG13(Page size), GPG14(Address cycle), GPG15(Bus width) – refer to PIN
CONFIGURATION), After power-on or system reset is occurred, the NAND Flash controller load automatically the
4-KBytes boot loader codes. After loading the boot loader codes, the boot loader code in steppingstone is
executed.
NOTE
During the auto boot, the ECC is not checked. So, the first 4-KB of NAND flash should have no bit error.