Zenith Data Systems MT2000 - Manual (Page 164)

6-21
Problem Solving
Table 6-3. POST Tests
Code Beeps POST Routine Description
02 1-1-1-3 Verify Real Mode
04 1-1-2-1 Get CPU type
06 1-1-2-3 Initialize system hardware
08 1-1-3-1 Initialize chipset registers with initial POST values
09 1-1-3-2 Set in POST flag
0A 1-1-3-3 Initialize CPU registers
0C 1-1-4-1 Initialize cache to initial POST values
0E 1-1-4-3 Initialize I/O
10 1-2-1-1 Initialize Power Management
11 1-2-1-2 Load alternate registers with initial POST values
12 1-2-1-3 Restore CPU control word during warm boot
14 1-2-2-1 Initialize keyboard controller
16 1-2-2-3 BIOS ROM checksum
18 1-2-3-1 8254 timer initialization
1A 1-2-3-3 8237 DMA controller initialization
1C 1-2-4-1 Reset Programmable Interrupt Controller
20 1-3-1-1 Test DRAM refresh
22 1-3-1-3 Test 8742 Keyboard Controller
24 1-3-2-1 Set ES segment register to 4 GB
28 1-3-3-1 Autosize DRAM
2A 1-3-3-3 Clear 512K base RAM
2C 1-3-4-1 RAM failure on address line xxxx*
2E 1-3-4-3 RAM failure on data bits xxxx* of low byte on memory bus
30 1-4-1-1 RAM failure on data bits xxxx* of high byte on memory bus
32 1-4-1-3 Test CPU bus-clock frequency
34 1-4-2-1 Test CMOS RAM
37 1-4-2-4 Reinitialize the chipset (MB only)
38 1-4-3-1 Shadow system BIOS ROM
39 1-4-3-2 Reinitialize the cache (MB only)
3A 1-4-3-3 Autosize cache
3C 1-4-4-1 Configure advanced chipset registers
3D 1-4-4-2 Load alternate registers with CMOS values
* If the BIOS detects error 2C, 2E, or 30 (base 512K RAM error), it
displays an additional word-bitmap (xxxx) indicating the address
line or bits that failed. For example, “2C 0002” means data bits 12
and 5 (bits 12 and 5 set) have failed in the lower 16 bits.