Rainbow Electronics ATmega128L - Manual (Page 113)

113
ATmega128(L)
2467B–09/01
Input Capture Unit The Timer/Counter incorporates an input capture unit that can capture external events
and give them a time-stamp indicating time of occurrence. The external signal indicating
an event, or multiple events, can be applied via the ICPn pin or alternatively, for the
Timer/Counter1 only, via the analog-comparator unit. The time-stamps can then be
used to calculate frequency, duty-cycle, and other features of the signal applied. Alter-
natively the time-stamps can be used for creating a log of the events.
The input capture unit is illustrated by the block diagram shown in Figure 47. The ele-
ments of the block diagram that are not directly a part of the input capture unit are gray
shaded. The small “n” in register and bit names indicates the Timer/Counter number.
Figure 47. Input Capture Unit Block Diagram
Note: The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not
Timer/Counter3.
When a change of the logic level (an event) occurs on the input capture pin (ICPn),
alternatively on the analog comparator output (ACO), and this change confirms to the
setting of the edge detector, a capture will be triggered. When a capture is triggered, the
16-bit value of the counter (TCNTn) is written to the input capture register (ICRn). The
input capture flag (ICFn) is set at the same system clock as the TCNTn value is copied
into ICRn register. If enabled (TICIEn = 1), the input capture flag generates an input
capture interrupt. The ICFn flag is automatically cleared when the interrupt is executed.
Alternatively the ICFn flag can be cleared by software by writing a logical one to its I/O
bit location.
Reading the 16-bit value in the input capture register (ICRn) is done by first reading the
low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high
byte is copied into the high byte temporary register (TEMP). When the CPU reads the
ICRnH I/O location it will access the TEMP register.
The ICRn register can only be written when using a waveform generation mode that uti-
lizes the ICRn register for defining the counter’s TOP value. In these cases the
waveform generation mode (WGMn3:0) bits must be set before the TOP value can be
ICFn (Int.Req.)
Analog
Comparator
WRITE ICRn (16-bit Register)
ICRnH (8-bit)
Noise
Canceler
ICPn
Edge
Detector
TEMP (8-bit)
DATABUS
(8-bit)
ICRnL (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
ACIC* ICNC ICES ACO*